Encoding system

ABSTRACT

An encoding circuit for retrieval apparatus wherein retrieval or access phrases are entered via an alphanumeric keyboard which converts each character into a m bit binary code. The phrases are then broken into segments of n characters each of which are logically compared with each other in a particular manner so that the first bit of the first segment&#39;&#39;s first character is compared with the first bit of the second segment&#39;&#39;s first character, etc. The results of this first comparison is then similarly compared with the character bits of the next segment, and the cycle is repeated for any additional segments.

United States Patent De Clerck et al.

[ 1 Sept. 5, 1972 54] ENCODING SYSTEM [72] Inventors: Robert D. De Clerck, Fairport; Glenn D. Smith, Rochester, both of 21 Appl. No.: 608,015

[52] US. Cl; ..340/347 DD, 235/154, 235/165 [51] Int. Cl. ..'..;..-.H03k 13/00 [58] Field of Search..... .340/347, 173,154, 152, 348;

12/1966 Sims, Jr. ..235/165 X 3,394,350 7/ 1968 Packard ..340/342 X 3,413,618- 11/1968 Shuba ..340/173 X Primary ExaminerMaynard R. Wilbur Assistant Examiner-Charles D. Miller Attorney-James T. Ralabate, Norman E. Schrader and Ronald Zibelli [57] ABSTRACT An encoding circuit for retrieval apparatus wherein retrieval or access phrases are entered via an alphanumeric keyboard which converts each character into a m bit binary code. The phrases are thenbroken into segments of n characters each of which are logically compared with each other in a particular manner so [56] keferencescited that the first bit of the first segments first character is v UNITED STATES EN compared with the first bit of the second segments 1 first character, etc. The results of this first comparison 3,106,636 10/1963 McIntyre et al. ..235/165 is then Similarly compared with the character bits f 3,194,951 7/1965 Schaefer ......340/347 x the next segment, and the cycle is repeated for any 3,237,170 2/1966 Blasbalg et a1 ..340/172.5 ditiona, segmem 3,247,365 4/1966 Dell et a1. ..235/165 X 3,271,517 9/1966 DeRosa ..340/347 X 9 Claims,- 6-Draw1ng Figures KEYBOARD b TIMING INPUT SHIFT REGISTER 7 DECISION STORAGE P SHIFT REGISTER OUTPUT a ADDER REGISTER CONVERTER I 'PIITEN'TEII EP SIIIZ Y 3.689.915

' SHEET 1 [IF 5 Q -2 4 w KEYBOARD TIMING INPUT $H|FT REGISTER DECISION STORAGE SHIFT REGISTER t /2 L J \I V I OUTPUT ADDER REGISTER CONVERTER 39 IULIUI INVENTOR.

GLENN D. SMITH ROBERT D. DECLERCK FIG. 2 W W ATTORNEYS PATENTEDSEP 51972 SHEET 2 BF 5 IN VEN TOR;

GLENN D. SMITH ROBERT D. DECLERCK A TTURNEYS P'A'TEN'TEDSEP 5 I972 SHEET t 0F 5 K c 0 mm WMD WWO. amt W B um; w m we aii o;u"u u u u"u uuuwuuuno uuo u u mwm wlw wwwwwwwww wwwww +T .Eim .PIQE IOF m mosa smz A 3.689.915

SHEET 5 BF 5 ENTER SUBDIVISON cove BITS 2ND, LATER,OR No STORE IN PARTIAL SUB STORAGE SR DIVISION 7 3 5 B|TS YES COMPARE A$ A BITS A-B+A-B-z STOREQZ lN' STORAGE s R A5 8 srrs ANY SUBDIV'SlONS TO OUTPUT REGISTER FIG. 7

BACKGROUND OF THE INVENTION This invention relates generally to improved encoding circuits, and, more particularly, to improved encoding circuits for random access retrieval systems.

There exists presently an ever-increasing need to very simply, quickly, and accurately retrieve information stored on randomly filed records, such as notchededge business cards.

With the advent of aperture cards and microimaging for storage purposes, the amount of information which can be stored creates a very large number of such records which can possibly be individually retrieved. The size of such storage dictates a preference that any retrieval system be able to retrieve only the desired record or card. Otherwise, with a large storage, the number of undesired cards closely similar to the desired card in retrieval code characteristics would significantlyimpair the speedand convenience of the retrieval system. In order to reduce or' completely eliminate this number of undesired cards, the preferred retrieval system should have a high order of uniqueness for each coded input which actuat es a mechanical retrieval apparatus. Such a uniqueness is possible wheneach access or descriptor word is accorded a retrieval code which is distinct and unique from the codes accorded all the other access words. While this total uniqueness-may objectively appear simple to accomplish, it presents a problem of some magnitude when each access or descriptor word code is examined subjectively by present day mechanical retrieval apparatus. Therefore, while access codes may be patently distinct and unique from each other, the subjective requirements of the mechanical retrieval apparatus used to actually select a card in accordance with such a code place a premium onthe degree of uniqueness and distinction among the codes.

It is very difficult to provide total or 100 per cent uniqueness when retrieving from a storage fileof any significant size. However, it isa preferred system which can afford 98 percent uniqueness with a file of 1000 retrievable cards, for example. Such a uniqueness means practically that for every 100 retrievals executed, the desired record or card, and only this card, will be retrieved 98 times. The other two retrievals will also provide the desired card but accompanied by some number of undesired cards.

While the desire of a high order of uniqueness can be satisfied with a very complicated encoding scheme wherein each character of the descriptor word or phrase is accorded a multi-elernent code, a compromise between uniqueness and complexity or cost is preferred. Therefore, maximum uniqueness with a reasonable code scheme is a desirable goal both from the standpoint of efficiency and expense.

In addition tothe desirability of a high order of uniqueness, it is further desirable to provide a retrieval encoder with an operator-machine interface which is simple, rapid, and economical. Such an interface should preferably allow the use of direct access or descriptor word entry. That is, the operator should be able to retrieve a progress report, for example, from the storage file by directly using the descriptor term Progress Report to enter the retrieval system. In this manner, the operator would not have to use the descriptor term in reference to a long and cumbersome list of descriptor words to determine the particular retrieval code accorded to the desired descriptor word. This would also permit an inexperienced operator to retrieve stored information with substantially the same facility and accuracy as an experienced operator.

Such an interface and the encoder system associated therewith should also. preferably accept access or descriptor words or phrases having varying character lengths to permit a great flexibility in choice of such words or phrases without compromising descriptiveness itself.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to improve encoding schemes.

It is another object of the present invention to provide an improved encoding circuit'which willaccept direct alphanumeric lengths.

Additionally, it is an object of the present invention to improve encoding circuits wherein the output thereof has'a maximum uniqueness associated with a corresponding input.

Still further, it is an object of the present invention to provide improved encoding circuits which are simple, efficient, and economical.

inputs of varying character mation will be of a uniform length and will result from adding sequential portions or segments of the coded words in accordance with an adding scheme which imparts maximum uniqueness to this final summation.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, features and advantages of the present invention may be apparent from the following detailed description of a preferred embodiment of the invention as illustrated in the accompanying drawings, wherein:

FIG. 1 is a block diagram of a system including the encoding circuit in accordance with the principles of the present invention;

FIG. 2 is an illustration of timing waveforms;

FIG. 3 illustrates schematically the keyboard coding matrix in accordance with the principles of the present invention;

FIG. 4 illustrates a timing control circuit;

FIG. 5 illustrates schematically the input register and decision and adding circuits in accordance with the principles of the present invention; and,

FIG. 6 illustrates schematically the storage shift reinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT Reference is now made in more detail to the block diagram of FIG. 1 wherein the overall system in which the encoding circuit of the present invention may be found.

A keyboard 2 is provided for the direct entry of alphanumeric information to be encoded and further utilized, for example, in a retrieval system. The keyboard 2 provides coded character information in accordance with the alphanumeric word or phrase entered via the character keyboard to a timing circuit 4 and input shift register circuit 6. It should be understood that the number of characters in an alphanumeric word or phrase may vary. However, for purposes of explanation, the number of alphanumeric characters in any access word or phrase will be referred to as q number of characters.

The timing circuit 4-acknowledges entry of alphanumeric information at the keyboard and commences a specific cycle of operation which will be described in more detail hereinafter. At this point, his sufiicient to understand that the timing circuit 4 provides the necessary timing and shift pulses to the other various circuits represented in FIG 1 in block form.

The particular alphanumeric information entered via keyboard 2 is stored a character at a time in the input shift register 6. The minimum number of stages of this input register 6 will be determined by the number of code bits used to designate a particular alphanumeric character at the keyboard. For purposes of explanation, this number of code bits may be referred to as m bits. Appropriate shift or clock pulses from the timing controlcircuit 4 will manipulate and clear the contents of the input shift register as a new character is entered at the keyboard. The contents of the input shift register 6 are shifted serially into a decision circuit 8. This decision circuit 8 will be explained in more detail hereinafter. It is sufficient to state at this point that the decision circuit 8 monitors the number of coded characters which are shifted through the input shift register 6 and will permit the first segment'of the word or descriptor phrase entered at the keyboard 2 to pass directly into the storage shift register 10. The number of characters in a segment will be determined by other parameters of the overall system which will be referred to in more detail hereinafter. For purposes of explanation, this number of characters per segment may be referred to as n characters. Therefore, a segment will have m times n number of code bits.

After this first segment of the access or descriptor word or phrase is loaded into the storage shift register 10 via the decision circuit 8, the latter will divert oneby-one the coded characters in the next segment of the descriptor word into an adder circuit 12. This adder circuit also will be described in more detail hereinafter.

Substantially contemporaneously with the diversion of the second segment into the adder circuit 12, the coded characters of the first segment of the descriptor word in the storage shift register are also shifted oneby-one into the adder circuit 12. This permitsthe adder circuit to add the first coded characters of the first and second segments in accordance with a particular adding scheme which will be referred to in more detail hereinafter. The summation of this operation in the adder circuit 12 is then loaded back into the storage shift register 10. This process is repeated for every coded character in the first and second segments. Upon the completion of this addition, the first coded character of the third segment or portion thereof is added in a similar operation to the already summed first characters of the first and second segment which a seen hereinafter, that the term add or addition or similar expression is used in this description in a special manner to denote a binary comparison of a particular nature other than conventional binary addition.

After subsequent segments of the access or descriptor word or phrase have been added'inconformance with the aforementioned operation to the summed first and second segments of this word or phrase and the summation of these segments has been loaded into the storage shift register l0, a suitable retrieve signal routed through the timing control circuit 4 from the keyboard 2 may initiate transfer of the summation serially into an output register 14 which is associated with a conventional converter circuit 16. The output register may be of any conventional design which is compatible with the type of conversion to be made in the converter circuit 16. This will be explained more fully with an example hereinafter in connection with the description of the specific circuit of the storage shift register 10.

Reference will now be made to the schematic diagram of FIG. 3 which shows symbolically a plurality of keyboard keys 18 which are shown with alphanumerical designations representative of the numbers 0 through 9 and the characters of the alphabet. In addition, two keys 20 and 22 have been designated clear and retrieve respectively. These keys 18, 20 and 22 are connected directly to ground potential and to a suitable sourceof negative potential applied at terminal 23 via a voltage-dropping lamp 25, for example.

Actuation of the clear key will generate an appropriate clear signal at terminal C which is utilized by the remaining portions of the encoding system in accordance with the present invention to clear all flipflops throughout the circuit. Depression of the retrieve key will generate a signal at terminal R which will initate the aforementioned conversion of the contents of the storage shift register 10, for further utilization, for example, by an appropriate mechanical retrieve apparatus. Depression of one of the alphanumeric keys 18 used letters such as U, V, W, X, Y, and Z" have been grouped effectively with one key since these lettered keys are all tied to one output terminal.

lowing code for the various alphanumeric characters:

1,A,B=000l 2, C,D=00l0 Therefore by the depression of any of these alphanumerical coded keys 18, a particular m-bit binary signal will be generated at the output terminals K,,,. It should beunderstood that while a four bit code is illustrated, any number of bits may be employed within reason to designate the alphanumeric characters. Also, while the table above sets forth a particular binary code for various alphanumeric characters, many other binary codes may be used in accordance with the principles of the present invention.

In addition, it should be noted that while there are m 1 output terminals K from the keyboard 2, only m bits are usedin the code in accordance with the present invention. This will be explained in more detail in connection with the description of the input shift register 6.

Detailed reference will now be made 101116 timing controlcircuit 4 of FIG. 4 in combination with'the timing waveform diagram of FIG. 2. A conventional OR gate 26 monitors the output terminals K from the keyboard 2 in FIG. 3 as well as the retrieve output terminal R. In this way whenever one of the alphanumeric keys 18 is depressed, OR gate 26 will pass a signal to a conventional delay circuit 28 which will provide a predetermined delay and then translate a signal to a conventional Schmitt trigger circuit 30. The output signal from the OR gate 26 is represented in exaggerated form in F IG, 2 as waveform 27. The duration of this pulse may typically be 30'milliseconds. This duration may be representative of the time an average keyboard operator holds a key in a depressed condition. The output from the Schmitt trigger 30 is shown as waveform 31 in FIG. 2 and the delay between the lead edges of waveforms 27 and 31 is typically milliseconds. The output from the Schmitt trigger 30 provides one input to an AND gate 32, the other input of which is supplied directly from the output of the OR gate 26. As shown in FIG. 4, the output waveform 31 from the Schmitt trigger 30 is also supplied to an output terminal S as well as to the clock input of the set side AND gate associated with a flip-flop 58.

The output pulse 31 at the terminal S will be hereinafter referred to as a strobe pulse and, as such, need only be considered as a positive-going signal or the lead edge of the pulse in waveform 31. Due to the inherent bounce" in the contacts associated with the keys 18 of the keyboard 2, the delay circuit 28 is preferable to insure that the strobe pulse is generated when the output signal from the output terminal K of the keyboard has stabilized. In addition, the preference for a fast rise time by the associated flipflops makes the Schmitt trigger a desirable component in the input of the multivibrator 36. The AND gate 32 is also preferred to prevent any noise from starting the clock generator '38.

However, these components are not necessary for successful operation of the preferred embodiment of the present invention.

The coincidence of the pulses in waveform 27 and waveform 31 at the inputs of AND gate 32 serve to ac-. tuate aconventional single shot multivibrator 36 which provides a slight delay of typically 0.5 milliseconds. The output of the multivibrator 36 is connected to the clock input of the set side AND gate associated with the flip-flop 34. Therefore, after a typical delay of approximately 0.5 milliseconds,theflip-flop 34 will be placed in a set condition by the coincidence of the output from the multivibrator 36 and the output from the OR gate 26 which is connected to the DC level input of the set side AND gate associated with this flip-flop 34. The setting of the flip-flop 34 initiates an output signal or clock enable signal as shown in FIG. 2 as waveform 35 which commences the generation of clock pulses in a conventional clock generator 38 typically shown in waveform 39 of FIG. 2. These clock pulses are present at the output terminal designated CL in FIG. 4. The flip-flop 34 will be reset upon the generation of a clock inhibit pulse which is supplied to input terminal CI as shown in FIG. 4. Upon the resetting of flip-flop 34 the generation of clock pulses at terminal CL is terminated. This clock inhibit pulse which is represented by waveform 40 in FIG. 2 is generated in the input shift register 6 which is shown in greater detail in FIG. 5.

Referring now in detail to FIG. 5, there is shown a conventional shift register 42 having m 1 number of stages. This provides one stage more than would be normally required to store the m bits per alphanumeric character. The shift register 42 is parallel loaded upon coincidence of the strobe pulse as shown in waveform 32 of FIG. 2 at input terminal S and appropriate signals from the output terminals K,,, of the keyboard 2 in FIG. 3.

While FIG. 3 indicated m 1 number of K terminals it will be understood from the code table hereinabove set forth that only m bits are required to appropriately designate various alphanumeric characters from the keyboard 2. In this table, the numeral zero and the alphanumeric characters U, .V, W, X, Y" and Z were all represented by the binary m bit code 0000. Therefore, by reviewing the diode arrangement in FIG. 3, it will be understood that the depression of any of these alphanumeric characters will present at the K output terminals the desired code 0000. Therefore, the output terminal related to these alphanumeric characters need not be connected as an inputto the input shift register 6 in FIG. 5. However, it is necessary that this terminal provide one input to OR gate 26 in the timing control circuit of FIG. 4 in order to initiate the clock pulses whenever one of these alphanumeric characters is selected by the operator via the keyboard.

gate associated with the set side of the flip-flop constituting the first stage of the shift register. As is shown,

the other DC level inputs of the remaining four stages of this shift register are connected to respective output terminals K associated with the keyboard 2. The clock input of the various stages of the shift register 42 is connected in common to input terminal S to which is supplied the strobe pulse. The shift pulses which effect the shifting of the contents in the various stages of the shift register from leftto right as FIG. isviewed are'supplied from the clock generator 38 of FIG. 4. A clear pulse 42 as seen in FIG. 2 which is supplied at input terminal CA in FIG. 5 resets all the stages in the shift register 42.

Therefore, in operation, the shift register 42 1 upon the depression of a particular key of the keyboard 2 in FIG. 3 will accept in its last four stages the four binary bits designated with the binary code accorded to that character associated with the depressed key. This depression of one of the keys in the keyboard 2 will generate the strobe pulse which effects this loading of the input shift register as hereinabove described. Also, shortly thereafter the clock generator will commence operation to provide four clock pulses which will effectively shift out serially the contents of the last four stages of the input shift register.

These four clock pulses will be generated in the clock generator 38 of FIG. 4 between a period initiated by a pulse from the output of multivibrator 36 and the receipt of a clock inhibit pulse at terminal CI which serves to reset flip-flop 34. This clock inhibit signal, as

noted hereinabove, is generated from the input shift register 6 in FIG. 5. More specifically, AND gate 44 serves to monitor a particular output of each of the m 1 stages of the shift register 42 so as to generate a clock inhibit pulse when the first four stages of this input shift register are in a reset condition and the last stage is in a set condition. In this manner, since the first stage of the input register 42 was automatically set by the coincidence of the strobe pulse at terminal S, after four shift pulses have arrived at terminal CL the binary one or set condition of the first stage of the shift register will have been shifted four stages to the last stage. Therefore, by monitoring the one or set side outputs of the first four stages along with the zero or reset side output of the last stage of the input shift register, AND gate 44 will generate a clock inhibit pulse when the first four stages are in a reset condition and the last stage is in a set condition. This clock inhibit pulse is delivered to output terminal CI in FIG. 5.

Referring again to the timing control circuit of FIG. 4 it will be seen that the clock inhibit pulse, in addition to resetting flip-flop 34, also provides one input to OR gate 46 which has an output designated at terminal CA.

, are delivered at terminal CL, after which time this bi- This output is provided as an input at a similarly designated terminal in FIG. 5 to effectively clear or reset all the stages of the input shift register in preparation for receipt of a new alphanumeric binary code signal from output terminals K of the keyboard in FIG. 3.

The clock inhibit signal and the clear or reset signal generated at output terminal CA inFIG. 4 are typically illustrated relative to the other waveforms generated in the timing control circuit in FIG. 2 and are designated waveforms 40 ans 43, respectively.

The serial output from the input shift register 6 in FIG. 5 is coupled to the adder circuit designated generally by the reference numeral 12. This adder circuit also receives inputs from the decision circuit generally designated by the reference numeral 8. Be-

' fore a detailed description of the operation of these two circuits is-set forth, it is desirable to describe in detail the storage shift register 10 which is illustrated schematically in FIG. 6. 1

1 Reference will now be made in detail to the storage shift register 10 in FIG. 6.,The storage shift register includes 17 stages or (m X n 1) number of stages where m is the number of binary bits' per character and n is the number of characters per segment as noted h'ereinabove. Right shift input pulses are provided from the clock generator described in FIG. 4 and are applied at terminal CL. At terminal CA clear or reset pulses are provided to clear or reset certain stages of the shift register. It will be recalled that the clear pulses at terminal CA were generated in response to either a clock inhibit signal. or a clear signal directly from the keyboard 2. The serial input to the storage shift register 10 is provided at tenninal SSR which is coupled to the output of the adder circuit as will be further explained hereinafter.

A serial output is taken from the storage shift register 10 at its 16th stage and is designated by terminals 16 and 16 An additional output is made from the one or set side of the 17th stage and is delivered at a terminal designated DE. It should also be noted that the terminal CA is connected to a set input of the first stage of the storage shift register so that this first stage is placed in a set condition or binary 1 when the entire storage register is cleared. This binary l in the first stage is used as a counting technique to indicate when 16 shift pulses nary 1 will be at the 17th stage and will provide a suitable signal indicative thereof at terminal DE. In the explanation hereinafter of the decision circuit, the utilization of this signal will be further explained.

Reference is again made to FIG. 5 and more particularly to the adder circuit 12. This adder circuit 12 ineludes two AND gates 48 and 50, the outputs of which are gated through a conventional OR gate 52. The output of this OR gate 52 is coupled to an output terminal designated SSR which is, in turn, coupled to the SSR input at the first stage of the storage shift register 10.

The two AND gates 48 and 50 are utilized to monitor the output of the 16th stage of the shift register and also the output of the last stage in the input shift register 6. It is these two AND gates which perform the addition or comparison which is preferable in accordance with the principles of the present invention in order to provide a high degree of uniqueness in the final summation which is stored in the storage shift register 10. More specifically, AND gate 48 has three inputs one of which is derived from the one or set side of the last stage of the input shift register 6. The second input to AND gate 50 is derived from the zero or reset side of flip-flop 54 which is in the decision circuit 8. The final input to this AND gate 48 is derived from the zero side or reset side output of the 16th stage of the storage shift register 10. Similarly, AND gate 50 monitors the zero or reset side of the last stage of the input shift register 6, the zero or reset side of the flip-flop 54 in the decision circuit 8, and the one or set side output of the 16th stage of the storage shift register.

Referring still to FIG. Sand more specifically to the adder circuit 12, it may be stressed that the particular binary logic utilized in this circuit implements the following Boolean expression:

where A is the output of the last stage of the input shift register and B is the output of the 16th stage of the storage shift register. it has been discovered that such a Boolean expression for adding? binary numbers results in a summation which does not tend to go to zero as wouldbe normally expected when using conventional binary addition. In this manner, the present invention provides a final coded summation represen- I put of the last stage of the'input shift register 6, the one or set side output of the flip-flop 54 in the decision circuit, and 'also the retrieve terminal R from the keyboard 2. As was noted hereinabove in connection with the block diagram of FIG. 1, the decision circuit determines when the first segment of a descriptor or access word or phrase is being entered via the keyboard-2 and sequentially passes the binary bits representative of this segment to the stages of the storage shift register 10. After this loading of the storage shift register has been completed with the first segment, the decision circuit will then interrupt this path from the input shift register to the storage shift register and commence the addition of the contents in the storage shift register with the characters in the next segment being entered via the keyboard 2. This, of course, is performed in the adder circuit previously described.

Flip-flop 54 is set by a positive-going signal at its set input which is supplied from the one or set side output of the last or 17th stage of the storage shift register of FIG. 6 at terminal DE. This positive-going signal will occur after the binary 1, which is loaded into the first stage of this shift register upon the clearing of all the remaining stages, is shifted through the 16 stages to the last stage indicating that 16 bits have been loaded into the storage shift register 10. When this happens, the decision enable pulse is generated at terminal DE which sets flip-flop '54. In the set condition, this flipflop disables AND gate 56 thereby interrupting the path between the input shift register 6 and the storage I shift register 10 via OR gate 52. While in its reset condition as it is initially and before receipt of the decision enable pulse at terminal DE, flip-flop 54 provides disabling signals to AND gates 48 and 50 in the adder circuit 12. This flip-flop 54 is reset either when the retrieve key at the keyboard 2 is depressed and the retrieval of the desired card is commanded or when the entire system is cleared by the depression of the clear key at the keyboard 2.

The cooperation of the circuits illustrated in the drawing may be more fully described by detailing a typical cycle of operation.

For purposes of this explanation it may be assumed that the operator desires to retrieve a data storage card or similar data storage medium bearing the descriptor or access term Progress Reports and a codeindicative thereof.

Before entering the access phrase, the operator may depress the clear key 20 on the keyboard 2 to clear all the stages of the various registers in the encoding system. This also insures that the first stage oflthe storage shift register 10 has as its contents a binary 1. Therefore, before entry of the access phrase the contents of the storage shift register in binary termsis:

The operator then depresses that key 18 representa tive of the first letter in the access phrase, viz., P, thereby strobing in parallel into the last four stages of the input shift register the code associated with the character P. As the strobe signal is generated in the timing control circuit 4, a binary one is entered automatically into the first stage of the input shift register 6 so that the contents of this register is:

It is noted that the contents of the various registers indicated in this description are associated with the first to the last stages going from left to right as shown in the drawing.

Very shortly after the first character code is strobed into the input shift register, the clock generator 38 is actuated thereby initiating a series of clock pulses which shift the contents of the input shift register four stages to the right. As the contents of the last four stages of this register .are shifted out they are translated via AND gate 56 in the decision circuit and OR gate 52 directly to the input of the storage shift register 10 which is also receiving clock pulses to shift the first character code into its first four stages such that the contents of the storage shift register is then:

After four clock pulses, AND gate 44 associated with the input shift register detects that four stages have shifted and generates a clock inhibit pulse thereby terminating operation of the clock generator 38. This clock inhibit pulse is also utilized to generate a clear or reset pulse via OR gate 46 in the timing control circuit 4 to clear the stages of the input shift register 6.

The encoding system of the present invention is then ready to receive a second character in the access phrase. The above-described cycle of operation for the first character P is repeated in a similar manner for the next three characters R, O and 6. After these three characters have been entered via the keyboard 2, the contents in the storage shift register is:

When the last stage, or 17th stage in the example, of the storage shift register received a binary l, flip-flop 54 inthe decision circuit is set thereby disabling AND gate 56 which served to pass the first four coded characters from the input shift register 6 to the storage shift register input. At the same time, this flip-flop 54 enables AND gates 48 and 50 in the adder circuit 12 to prepare for the next coded character in the access phrase.

The next coded character inputed via the keyboard 2' will be treated in a similar manner as noted hereinabove by the input shift register; However, the

'clockpulses which are delivered both to the input shift register and the storage shift register will effectively shift the contents of the shift registers serially to the adder circuit 12 which has now been enabled by the set condition of flip-flop 54 in the decision circuit. Y

The adder circuit 12, therefore, will receive serially the-contents of the input shift register and the contents of the storage shift register as they are shifted past the 16th stage thereof and perform a particular binary comparison. This comparison can be described in Boolean algebra as:

Z= Z1? A-B whereA is the output of the last stage of the input shift register and B is the output of the 16th stage of the storage shift register.

This summation is shifted bit-by-bit for each clock pulse into the first four stages of the storage shift register. This makesthe contents of the storage shift register:

The contents of the 17th stage of the storage shift register may be either one or zero depending upon the situation. i

The above described comparison cycle is repeated for the last three characters in the second segment of the access phrase, viz., E, S, and S. Therefore,

after the first eight characters of the access phrase have been entered via the keyboard and the comparison made by the adder circuit, the contents of the storage shift register becomes: I

Again, the contents of the 17th register upon 'the particular situation. g

The above described comparison cycle involving the first and second segments of the access phrase .will now be repeated using the contents of the storage shift re- This Boolean expression can also be represented in I binary terms by the following comparison table:

At each of the next four clock pulses generated after the strobing into the input shift register of the fifth character G, the contents (A) of the fifth, fourth, third, and second stages of the input shift register 6 are compared by the adder circuit 12 with the contents (B) of the 16th, 15th, 14th, and 13th stages of the storage shift register 10, respectively; This comparison, in accordance with the above comparison table, results in a four bit summation:

gister and the third segment which would include the characters R, E, P,a'nd 0. After this comparison in the adder circuit between the third segment and the contents of the storage shift register, the storage shift register has as its contents:

101 l/l000/l000/0ll1l- Again, the comparison cyclehereinabove described is repeated using the present contents of the storageshift register and the fourth segment which, with this particular access phrase, contains only three characters R, T, and S. After the character S has been compared with the contents of the storage shift register, and the result of this comparison is loaded into the storage shift register, the contents of this register then becomes:

llll/ll 10/0000/101 l/ I The binary number now'contained in the first 16 stages of the storage shift'register 10 represents a progressive comparison according to the aforementioned comparison table of sequential segments of the access phrase. Graphically this comparison may be seen as follows:

PROG ggss The result of this comparison is then compared to:

REPO

The results of this comparison is then further compared in a similar manner to:

RTS-- After this final comparison has been made, the operator has entered the entire access phrase Progress Reports and is ready to commence the actual retrieval operation. This is done by depressing the retrieve key 'w111 ,depend' 13 22 on the keyboard. Depression of this key will generate an output signal from the OR gate 26 in the timing control circuit of FIG.4 which willinitiate operation of the clock generator 38. In addition, the retrieve signal will set flip-flop 58 in the timing control circuit 4 which will serve to inhibit the resetting of flipflop 34 which controls the operation of the clock generator 38. In this manner, any clock inhibit signal generated by AND gate 44 associated ,with the input shift register 6 of PK}. will have no-effect upon the generation of the clock pulses at terminal CL. These clock pulses will continue to shift out of the storage shift register the aforementioned 16 bit binary number which is the total comparative result.

Also, the signal generated by the depression of the retrieve key 22 will reset flip-flop 54in the decision circuit thereby disabling the adder circuit 12. This retrieve signal is also coupled as one input to AND gate 56 which-acts to translate binaryinformation from-the input shift register to the storage shift register. Theregisters from each other.

Referringnow to FIG. 1 it will be recalled that the contents of the storage shift register, after the encoding has been completed, may be shifted to an output register 14 of the conventional design which is suited to the particular type of converter and retrieval mechanism utilized. For example, the output register may comprise four stages to permit a binary to decimal conversion which can be utilized in a conventional converter 16 to perform the actual retrieval process. Obviously, various counters and gates will be utilized to do not form part of the present invention per se and are included in this description for purposes of example only,

In summary, there has been described a novel and improved encoding system which permits adirect entry of alphanumeric character assess phrases. These phrases are binary coded'and subdivided into segments of a desired length which are then compared according to a preferred comparison table to provide a sequence of binary bits unique to the entered access phrase.

While the invention has been described with reference to the circuit disclosed herein, it is not confined to the details set forth since it is apparent that electrical equivalent components may be substituted for the components of the preferred circuit without departing from the scope of the invention. Thus, for example, although an additional stage is utilized in the input shift register 6 and the storage shift register 10 to provide a counting operation, it is readily apparent that a separate counter may be utilized to perform this same function, thus reducing the number of stages in these shift registers by one.

Also, while a particular key grouping of keyboard 2 has been illustrated and described, other combinations ing from the scope of this invention.

Similarly, while the present circuit has been illustrated and described as providing an input to an output register and a converter associated with a mechanical retrieval apparatus, it would be within the scope of the present invention to utilize the binary comparative result in the storage shift register for other purposes where a unique order of binary bits are needed which uniquely correspond with a particular access phrase.

Therefore, it is intended that the present invention cover such modifications or changes as may come within the scope of the invention as defined by the following claims.

What is claimed is:

1. An encoding system comprising:

a. an alphanumeric-to-m binary bit converter having converter output terminals;

a selectively actuatable source of clock pulses having an actuating input terminal and a clock output terminal;

. clock control circuit generating an actuating signal and a strobe pulse in response to a signal at said converter output terminals;

an input shift register having at least m number of input stages, a serial output terminal, and a shift input terminal, each of said input stages having a strobe input terminal and a binary input terminal;

e. first coupling means for coupling each of said converter output terminals individually to a binary input terminal of a respective input stage;

f. second coupling means for coupling said strobe pulse to said strobe input terminals and for coupling said clock output terminal to said shift input terminal;

. third coupling means for coupling said actuating signal to said actuating input terminal;

. a storage shift register having a least m X n number of storage stages, a serial output terminal, a serial input terminal, and a shift input terminal, said shift input terminal beingcoupled to said clock output terminal;

. transfer circuit means normally enabled and adapted to be disabled for coupling said serial output terminal of said input shift register to said serial input terminal of said storage shift register only when said transfer circuit means is enabled;

j. logic circuit means normally disabled and adapted to be enabled and having a comparison output terminal coupled to said serial input terminal of said storage shift register for making .a logic comparison of the binary outputs at said serial output terminals of said input and storage shift registers only when said logic circuit means is enabled; and,

' k. decision circuit means responsive to the arrival of m X n number of said clock pulses at the shift input terminal of said storage shift register for disabling said transfer circuit means and enabling said logic comparison circuit means.

2. An encoding system defined in claim 1 wherein said logic comparison circuit includes binary comparison means for effecting the following Boolean expression:

where A is the signal at said serial output terminal of said input shift register, B is the signal at said serial output terminal of said storage shift register, and Z is the result of said logic comparison delivered to said comparison output terminal.

3. An encoding system as defined in claim 2 further including:

a. deactuating circuit means responsive to m number of said clock pulses at said shift input terminal of said input shift register for generating a deactuating signal; and,

I b. fourth coupling means for coupling said deactuating signal to said actuating input terminal of said source.

4. An encoding system as described in claim 1 wherein said alphanumeric-to-m binary bit converter includes a keyboard apparatus having alphanumeric keys each of which are accorded a m-bit binary code.

5. An encoding system as defined in'claim 3 wherein said alphanumeric-to-m binary bit converter includes an alphanumeric keyboard, the keys of which are each accorded a m bit binary code.

6. An encoding system as defined in claim 5 wherein more than one of said keys are accorded the same m bit binary code. v

7. A circuit for generating a unique group of m X n sequence of q number of groups of m number of binary bits, said circuit comprising:

aja data input terminal adapted for receiving binary information;

b. storage means having at least m X n number of stages for storing in the sequence received at said data input terminal the first m X n number of binary bits of the total q X m number of binary bits;

- number of electrical signals which represent a specific d. transfer circuit means coupled to said data input terminal and responsive to the storage of said first m X n number of binary bits in said storage means for translating the remaining binary bits of said total q X m number of binary bits to said first input terminal of said logic comparison means in the sequence received at said data input terminal;

e. coupling means coupled between said storage means and said second input terminal for translating the binary bits stored in said m X n'stages in the sequence stored to said second input terminal; and,

f. translation circuit means coupled between said logic comparison means and said storage means for translating said output comparison signals in the sequence generated to said m X n stages. 7

8. A circuit as defined in claim 7 including clock generator means coupled to said input terminal, said storage means, and said coupling means for providing coincidence between the binary bits translated from said storage means and said input terminal to said logic comparison means.

9. A circuit as defined in claim 7 wherein said logic comparison means implements the following Boolean expression: Z 1

where Z is the said output comparison signal, A is the binary bit at said first input terminal, and B is the binary 

1. An encoding system comprising: a. an alphanumeric-to-m binary bit converter having converter output terminals; b. a selectively actuatable source of clock pulses having an actuating input terminal and a clock output terminal; c. clock control circuit generating an actuating signal and a strobe pulse in response to a signal at said converter output terminals; d. an input shift register having at least m number of input stages, a serial output terminal, and a shift input terminal, each of said input stages having a strobe input terminal and a binary input terminal; e. first coupling means for coupling each of said converter output terminals individually to a binary input terminal of a respective input stage; f. second coupling means for coupling said strobe pulse to said strobe input terminals and for coupling said clock output terminal to said shift input terminal; g. third coupling means for coupling said actuating signal to said actuating input terminal; h. a storage shift register having a least m X n number of storage stages, a serial output terminal, a serial input terminal, and a shift input terminal, said shift input terminal being coupled to said clock output terminal; i. transfer circuit means normally enabled and adapted to be disabled for coupling said serial output terminal of said input shift register to said serial input terminal of said storage shift register only when said transfer circuit means is enabled; j. logic circuit means normally disabled and adapted to be enabled and having a comparison output terminal coupled to said serial input terminal of said storage shift register for making a logic comparison of the binary outputs at said serial output terminals of said input and storage shift registers only when said logic circuit means is enabled; and, k. decision circuit means responsive to the arrival of m X n number of said clock pulses at the shift input terminal of said storage shift register for disabling said transfer circuit means and enabling said logic comparison circuit means.
 2. An encoding system defined in claim 1 wherein said logic comparison circuit includes binary comparison means for effecting the following Boolean expression: Z A.B + A.B where A is the signal at said serial output terminal of said input shift register, B is the signal at said serial output terminal of said storage shift register, and Z is the result of said logic comparison delivered to said comparison output terminal.
 3. An encoding system as defined in claim 2 further including: a. deactuating circuit means responsive to m number of said clock pulses at said shift input terminal of said input shift register for generating a deactuating signal; and, b. fourth coupling means for coupling said deactuating signal to said actuating input terminal of said source.
 4. An encoding system as described in claim 1 wherein said alphanumeric-to-m binary bit converter includes a keyboard apparatus having alphanumeric keys each of which are accorded a m-bit binary code.
 5. An encoding system as defined in claim 3 wherein said alphanumeric-to-m binary bit converter includes an alphanumeric keyboard, the keys of which are each accorded a m bit binary code.
 6. An encoding system as defined in claim 5 wherein more than one of said keys are accorded the same m bit binary code.
 7. A circuit for generating a unique group of m X n number of electrical signals which represent a specific sequence of q number of groups of m number of binary bits, said circuit comprising: a. a data input terminal adapted for receiving binary information; b. storage means having at least m X n number of stages for storing in the sequence received at said data input terminal the first m X n number of binary bits of the total q X m number of binary bits; c. logic comparison means having first and second input terminals for generating output comparison signals representative of a logic comparison of binary bits at said first and second input terminals; d. transfer circuit means coupled to said data input terminal and responsive to the storage of said first m X n number of binary bits in said storage means for translating the remaining binary bits of said total q X m number of binary bits to said first input terminal of said logic comparison means in the sequence received at said data input terminal; e. coupling means coupled between said storage means and said second input terminal for translating the binary bits stored in said m X n stages in the sequence stored to said second input terminal; and, f. translation circuit means coupled between said logic comparison means and said storage means for translating said output comparison signals in the sequence generated to said m X n stages.
 8. A circuit as defined in claim 7 including clock generator means coupled to said input terminal, said storage means, and said coupling means for providing coincidence between the binary bits translated from said storage means and said input terminal to said logic comparison means.
 9. A circuit as defined in claim 7 wherein said logic comparison means implements the following Boolean expression: Z A.B + A.B where Z is the said output comparison signal, A is the binary bit at said first input terminal, and B is the binary bit at said second input terminal. 